The present disclosure relates to a direct bond method and to a direct bond method that provides for thermal expansion matched devices for true heterogeneous three-dimensional integration.
Many currently used infrared sensor chip assemblies include silicon readout integrated circuits (ROIC) that are hybridized to mercury cadmium tellurium (HgCdTe) detector arrays using indium (In) bumps. Problems with such assemblies exist, however, in that these indium bumps tend to fail as a result of their inability to survive the large number of thermal cycles required for the assembly processes due to the coefficient of thermal expansion (CTE) mismatch between silicon (Si) and the HgCdTe.
While previous attempts to address these problems have been attempted, none are completely useful or satisfactory. For example, for indium bump (IB) focal plane arrays (FPAs), the approach has been to attempt to CTE match the ROIC to a detector by adhesively bonding titanium (Ti) and silicon (Si) shims to the back of a sensor chip assembly (SCA) after dicing and hybridization. While this approach can be effective, it is an expensive die-level process and is performed manually by skilled labor.
As another example, for heterogeneous three-dimensional (3D) integration, approaches include epitaxial growth of III-V semiconductor materials, such as gallium nitride (GaN), on a silicon (Si) substrate using buffer layers to provide the lattice match, or ultrasonically bonding a bonded completed III-V die to a silicon (Si) circuit. In both of these cases, III-V layers can tend to cause degraded performance due to stress associated with CTE mismatches between the III-V devices and silicon (Si) substrates.